(1) Field of the Invention
The present invention relates to a method used to fabricate semiconductor memory devices, and more specifically to a method used to create a polysilicon plug structure, used interconnect a bit line structure, to an underlying transfer gate transistor.
(2) Description of Prior Art
The trend to continually shrink dynamic random access memory, (DRAM), chips, necessitates the use of more sophisticated structures, used to connect overlying metal or polysilicon structures, such as bit lines, to underlying device components, such as source and drain regions of transfer gate transistors. One approach used by semiconductor designers and engineers is the use of a polysilicon plug structure, placed between bit line structures and underlying transfer gate transistor components. However the polysilicon plug, designed with minimum dimensions to satisfy the goal of micro-miniaturization, presents an alignment problem when attempting to place an overlying bit line structure on the top surface of an underlying polysilicon plug structure. One solution to the problem of placing a bit line structure, on a underlying polysilicon plug structure, is the addition of a landing pad shape, formed between the underlying polysilicon plug and the overlying bit line structure. The landing pad shape, larger in surface area than the polysilicon plug, allows an easier target for a subsequent overlying bit line structure, to contact. However the additional processing needed to create the landing pad shape, and the difficulty in aligning the landing pad shape to the smaller, underlying polysilicon plug shape, still suggest other needed solutions for bit line to transfer gate transistor connection.
This invention will offer a solution for successfully overlying a bit line structure to an underlying transfer gate transistor, via the formation of a modified polysilicon plug structure, featuring a two shaped polysilicon structure. The bottom shape of the modified polysilicon plug structure, is a narrow polysilicon plug, contacting an underlying source and drain region, of a transfer gate transistor. The upper shape of the modified polysilicon plug structure, is a polysilicon filled trench shape, larger in area than the underlying polysilicon plug, but created simultaneously with the smaller area, polysilicon plug, thus eliminating the need for the difficult alignment of the landing pad to the small area, underlying polysilicon plug structure. An important feature of this invention is the definition of the initial pattern of the trench, in an silicon oxide layer, via conventional photolithographic and anisotropic dry etching procedures, followed by an exposure to an isotropic wet etch, resulting in an enlargement of the trench. A second phase consists of defining the small opening in the silicon oxide layer, within the enlarged trench shape, needed to except the polysilicon plug structure. Polysilicon deposition and patterning, now result in the modified polysilicon plug structure, comprised of a polysilicon filled trench, overlying a narrower polysilicon plug. Prior art such as Hsu, in U.S. Pat. No. 5,552,343, describes a process for forming a tapered contact hole, via a wet etch, followed by a smaller hole, obtained via an anisotropic dry etch procedure. However this prior art does not use anisotropic dry etching for definition of both the larger and smaller diameter openings, nor does this prior art describe a method for creating the modified polysilicon plug structure, described in this invention.